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Chapter 0 Reader's Guide0.1 Outline of the Book0.2 A Roadmap For Readers and Instructors0.3 Why Study Computer Organization and Architecture0.4 Internet and Web ResourcesPART ONE OVERVIEW Chapter 1 Introduction1.1 Organization and Architecture1.2 Structure and Function1.3 Key Terms and Review QuestionsChapter 2 Computer Evolution and Performance2.1 A Brief History of Computers2.2 Designing for Performance2.3 The Evolution of the Intel x86 Architecture2.4 Embedded Systems and the ARM2.5 Performance Assessment2.6 Recommended Reading and Web Sites2.7 Key Terms, Review Questions, and ProblemsPART TWO THE COMPUTER SYSTEM Chapter 3 A Top-Level View of Computer Function and Interconnection3.1 Computer Components3.2 Computer Function3.3 Interconnection Structures3.4 Bus Interconnection3.5 PCI3.6 Recommended Reading and Web Sites3.7 Key Terms, Review Questions, and Problems3A Timing Diagrams Chapter 4 Cache Memory4.1 Computer Memory System Overview4.2 Cache Memory Principles4.3 Elements of Cache Design4.4 Pentium 4 Cache Organization4.5 ARM Cache Organization4.6 Recommended Reading4.7 Key Terms, Review Questions, and ProblemsAppendix 4A Performance Characteristics of Two-Level Memorie Chapter 5 Internal Memory Technology5.1 Semiconductor Main Memory5.2 Error Correction5.3 Advanced DRAM Organization5.4 Recommended Reading and Web Sites5.5 Key Terms, Review Questions, and ProblemsChapter 6 External Memory6.1 Magnetic Disk6.2 RAID6.3 Optical Memory6.4 Magnetic Tape6.5 Recommended Reading and Web Sites6.6 Key Terms, Review Questions, and ProblemsChapter 7 Input/Output7.1 External Devices7.2 I/O Modules7.3 Programmed I/O7.4 Interrupt-Driven I/O7.5 Direct Memory Access7.6 I/O Channels and Processors7.7 The External Interface: FireWire and Infiniband7.8 Recommended Reading and Web Sites7.9 Key Terms, Review Questions, and Problems Chapter 8 Operating System Support8.1 Operating System Overview8.2 Scheduling8.3 Memory Management8.4 Pentium Memory Management8.5 ARM Memory Management8.6 Recommended Reading and Web Sites8.7 Key Terms, Review Questions, and Problems Chapter 9 Computer Arithmetic9.1 The Arithmetic and Logic Unit (ALU)9.2 Integer Representation9.3 Integer Arithmetic9.4 Floating-Point Representation9.5 Floating-Point Arithmetic9.6 Recommended Reading and Web Sites9.7 Key Terms, Review Questions, and Problems Chapter 10 Instruction Sets: Characteristics and Functions10.1 Machine Instruction Characteristics10.2 Types of Operands10.3 Intel x86 and ARM Data Types10.4 Types of Operations10.5 Intel x86 and ARM Operation Types10.6 Recommended Reading10.7 Key Terms, Review Questions, and Problems Chapter 11 Instruction Sets: Addressing Modes and Formats11.1 Addressing11.2 x86 and ARM Addressing Modes11.3 Instruction Formats11.4 x86 and ARM Instruction Formats11.5 Assembly Language11.6 Recommended Reading11.7 Key Terms, Review Questions, and Problems Chapter 12 Processor Structure and Function12.1 Processor Organization12.2 Register Organization12.3 The Instruction Cycle12.4 Instruction Pipelining12.5 The x86 Processor Family12.6 The ARM Processor12.7 Recommended Reading12.8 Key Terms, Review Questions, and Problems Chapter 13 Reduced Instruction Set Computers (RISCs)13.1 Instruction Execution Characteristics13.2 The Use of a Large Register File13.3 Compiler-Based Register Optimization13.4 Reduced Instruction Set Architecture13.5 RISC Pipelining13.6 MIPS R400013.7 SPARC13.8 The RISC versus CISC Controversy13.9 Recommended Reading13.10 Key Terms, Review Questions, and Problems Chapter 14 Instruction-Level Parallelism and Superscalar Processors14.1 Overview14.2 Design Issues14.3 Pentium 414.4 ARM Cortex-A814.5 Recommended Reading14.6 Key Terms, Review Questions, and ProblemsPART FOUR THE CONTROL UNIT Chapter 15 Control Unit Operation15.1 Micro-operations15.2 Control of the Processor15.3 Hardwired Implementation15.4 Recommended Reading15.5 Key Terms, Review Questions, and ProblemsChapter 16 Microprogrammed Control16.1 Basic Concepts16.2 Microinstruction Sequencing16.3 Microinstruction Execution16.4 TI 880016.5 Recommended Reading16.6 Key Terms, Review Questions, and ProblemsPART FIVE PARALLEL ORGANIZATION Chapter 17 Parallel Processing17.1 The Use of Multiple Processors17.2 Symmetric Multiprocessors17.3 Cache Coherence and the MESI Protocol17.4 Multithreading and Chip Multiprocessors17.5 Clusters17.6 Nonuniform Memory Access Computers17.7 Vector Computation17.8 Recommended Reading and Web Sites17.9 Key Terms, Review Questions, and Problems Chapter 18 Multicore Computers18.1 HardwarePerformance Issues18.2 Software Performance Issues18.3 Multicore Organization18.4 Intel x86 Multicore Organization18.5 ARM11 MPCore18.6 Recommended Reading and Web Sites18.7 Key Terms, Review Questions, and ProblemsAPPENDIX A Projects for Teaching Computer Organization andArchitecture A.1 Interactive SimulationsA.2 Research ProjectsA.3 Simulation ProjectsA.4 Reading/Report AssignmentsA.5 Writing AssignmentsA.6 Test BankAppendix B Assembly Language, Assemblers, and CompilersB.1 Assembly LanguageB.2 AssemblersB.3 Loading and LinkingB.4 Recommended Reading and Web SiteB.5 Key Terms, Review Questions, and ProblemsONLINE CHAPTERSWilliamStallings.com/COA/COA8e.htm lChapter 19 Number Systems19.1 The Decimal System19.2 The Binary System19.3 Converting between Binary and Decimal19.4 Hexadecimal Notation19.5 Key Terms, Review Questions, and Problems Chapter 20 Digital Logic20.1 Boolean Algebra20.2 Gates20.3 Combinational Circuits20.4 Sequential Circuits20.5 Programmable Logic Devices20.6 Recommended Reading and Web Site20.7 Key Terms and Problems Chapter 21 The IA-64 Architecture21.1 Motivation21.2 General Organization21.3 Predication and Speculation21.4 IA-64 Instruction Set Architecture21.5 Itanium Organization21.6 Recommended Reading and Web Sites21.7 Key Terms, Review Questions, and ProblemsONLINE APPENDICESWilliamStallings.com/COA/COA8e.htmlAppendix C Hash Tables Appendix D Victim CacheAppendix E Interleaved MemoryAppendix F International Reference AlphabetAppendix G Virtual Memory Page Replacement AlgorithmsAppendix H Recursive ProceduresAppendix I Additional Instruction Pipeline TopicsH.1 Pipeline Reservation TablesH.2 Reorder BuffersH.3 ScoreboardingH.4 Tomasulo's AlgorithmReferencesGlossaryIndexAcronyms |
