Network systems design : using network processors : Intel IXP version / Douglas E. Comer.
Material type:
TextPublication details: New Delhi : Pearson/Prentice Hall, 2004Description: xxiv, 515 p. ill. ; 25 cmISBN: - 9788178089942
- 004.65 22 C7325
| Item type | Current library | Call number | Status | Date due | Barcode | |
|---|---|---|---|---|---|---|
Books
|
UE-Central Library | 004.65 C7325 (Browse shelf(Opens below)) | Available | T87 | ||
|
Books
|
UE-Central Library | 004.65 C7325 (Browse shelf(Opens below)) | Available | T11404 | ||
|
Books
|
UE-Central Library | 004.65 C7325 (Browse shelf(Opens below)) | Available | T4778 | ||
|
Books
|
UE-Central Library | 004.65 C7325 (Browse shelf(Opens below)) | Available | T1636 |
includes bibliography and index
1. Introduction and Overview. 2. Basic Terminology and Example Systems. 3. Review Of Protocols and Packet Formats. 4. Conventional Computer Hardware Architecture. 5. Basic Packet Processing: Algorithms and Data Structures. 6. Packet Processing Functions. 7. Protocol Software on a Conventional Processor. 8. Hardware Architectures for Protocol Processing. 9. Classification and Forwarding. 10. Switching Fabrics. 11. Network Processors: Motivation and Purpose. 12. The Complexity of Network Processor Design. 13. Network Processor Architectures. 14. Issues in Scaling a Network Processor. 15. Examples Of Commercial Network Processors. 16. Languages Used for Classification. 17. Design Tradeoffs and Consequences. 18. Overview of The Intel Network Processor. 19. Embedded RISC Processor (strongarm Core). 20. Packet Processor Hardware (Microengines And FBI). 21. Reference System and Software Development Kit (Bridal Veil, SDK). 22. Programming Model (ACE). 23. ACE Run-Time Structure and strongarm Facilities. 24. Microengine Programming I. 25. Microengine Programming II. 26. An Example ACE. 27. Intel's Second Generation Processors.
There are no comments on this title.
