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Digital design and computer architecture / (Record no. 672)

MARC details
000 -LEADER
fixed length control field 08495cam a2200241 a 4500
001 - CONTROL NUMBER
control field 1909
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20200706113303.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 060914s2007 ne a b 001 0 eng
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9788131215173
040 ## - CATALOGING SOURCE
Transcribing agency PK
082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.381
Edition number 22
Item number H3131
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Harris, David Money.
245 10 - TITLE STATEMENT
Title Digital design and computer architecture /
Statement of responsibility, etc David Money Harris, Sarah L. Harris.
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc New Delhi :
Name of publisher, distributor, etc Morgan Kaufmann Publishers,
Date of publication, distribution, etc 2008
300 ## - PHYSICAL DESCRIPTION
Extent xxii, 569 p.
Other physical details ill. ;
Dimensions 23 cm.
500 ## - GENERAL NOTE
General note Includes bibliographical references (p. 555-556) and index.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Digital electronics.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer architecture.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Harris, Sarah L.
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Books
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note 1. Table of Contents<br/>2. Preface<br/>3. Foreword<br/>4. Acknowledgments<br/>5. Introduction<br/>1 From Zero to One<br/>1.1 The Game Plan.<br/>1.2 The Art of Managing Complexity<br/>1.2.1 Abstraction<br/>1.2.2 Discipline <br/>1.2.3 The -Y¿s <br/>1.3 The Digital Abstraction <br/>1.4 Number Systems<br/>1.4.1 Decimal Numbers <br/>1.4.2 Binary Numbers <br/>1.4.3 Hexadecimal Numbers <br/>1.4.4 Bytes, Nibbles, and All That Jazz <br/>1.4.5 Binary Addition <br/>1.4.6 Signed Binary Numbers <br/>1.5 Logic Gates<br/>1.5.1 NOT Gate<br/>1.5.2 Buffer<br/>1.5.3 AND Gate <br/>1.5.4 OR Gate <br/>1.5.5 Other 2-Input Gates <br/>1.5.6 Multiple-Input Gates <br/>1.6 Logic Levels<br/>1.6.1 Supply Voltage<br/>1.6.2 Logic Levels <br/>1.6.3 Noise Margins <br/>1.6.4 DC Transfer Characteristics <br/>1.6.5 The Static Discipline <br/>1.7 * CMOS Transistors <br/>1.7.1 Semiconductors<br/>1.7.2 Diodes <br/>1.7.3 Capacitors <br/>1.7.4 nmos and pmos Transistors <br/>1.7.5 CMOS NOT Gate <br/>1.7.6 Other CMOS Logic Gates <br/>1.7.7 Transmission Gates<br/>1.7.8 Pseudo-nmos Logic <br/>1.8 * Power Consumption<br/>1.9 Summary and A Look Ahead<br/>2 Combinational Logic Design<br/>2.1 Introduction.<br/>2.2 Boolean Equations<br/>2.2.1 Terminology <br/>2.2.2 Sum-of-Products Form<br/>2.2.3 Product-of-Sums Form<br/>2.3 Boolean Algebra<br/>2.3.1 Axioms <br/>2.3.2 Theorems of One Variable <br/>2.3.3 Theorems of Several Variables<br/>2.3.4 The Truth Behind It All <br/>2.3.5 Simplifying Equations <br/>2.4 From Logic to Gates<br/>2.5 Multilevel Combinational Logic<br/>2.5.1 Hardware Reduction <br/>2.5.2 Bubble Pushing<br/>2.6 X's and z's, Oh My.<br/>2.6.1 Illegal Value: X<br/>2.6.2 Floating Value: Z<br/>2.7 Karnaugh Maps<br/>2.7.1 Circular Thinking<br/>2.7.2 Logic Minimization with K-Maps <br/>2.7.3 Don¿t Cares<br/>2.7.4 The Big Picture<br/>2.8 Combinational Building Blocks<br/>2.8.1 Multiplexers <br/>2.8.2 Decoders <br/>2.9 Timing<br/>2.9.1 Propagation and Contamination Delay <br/>2.9.2 Glitches <br/>2.10 Summary<br/>3 Sequential Logic Design <br/>3.1 Introduction<br/>3.2 Latches and Flip-Flops<br/>3.2.1 SR Latch <br/>3.2.2 D Latch <br/>3.2.3 D Flip-Flop <br/>3.2.4 Register <br/>3.2.5 Enabled Flip-Flop<br/>3.2.6 Resettable Flip-Flop<br/>3.2.7 *Transistor-Level Latch & Flip-Flop Designs <br/>3.2.8 Putting It All Together <br/>3.3 Synchronous Logic Design<br/>3.3.1 Some Problematic Circuits <br/>3.3.2 Synchronous Sequential Circuits <br/>3.3.3 Synchronous And Asynchronous Circuits <br/>3.4 Finite State Machines<br/>3.4.1 FSM Design Example<br/>3.4.2 State Encodings <br/>3.4.3 Moore and Mealy Machines <br/>3.4.4 Factoring State Machines <br/>3.4.5 FSM Review <br/>3.5 Timing of Sequential Logic.<br/>3.5.1 The Dynamic Discipline <br/>3.5.2 System Timing <br/>3.5.3 * Clock Skew <br/>3.5.4 Metastability <br/>3.5.5 Synchronizers <br/>3.5.6 * Derivation of Resolution Time <br/>3.6 Parallelism<br/>3.7 Summary.<br/>4 Hardware Description Languages<br/>4.1 Introduction<br/>4.1.1 Modules<br/>4.1.2 Language Origins <br/>4.1.3 Simulation and Synthesis <br/>4.2 Combinational Logic<br/>4.2.1 Bitwise Operators<br/>4.2.2 Comments and White Space <br/>4.2.3 Reduction Operators <br/>4.2.4 Conditional Assignment <br/>4.2.5 Internal Variables <br/>4.2.6 Precedence <br/>4.2.7 Numbers<br/>4.2.8 Z¿s and X¿s <br/>4.2.9 bit swizzling<br/>4.2.10 Delays <br/>4.2.11 * VHDL Libraries and Types <br/>4.3 Structural Modeling<br/>4.4 Sequential Logic.<br/>4.4.1 Registers<br/>4.4.2 Resettable Registers<br/>4.4.3 Enabled Registers<br/>4.4.4 Multiple Registers<br/>4.4.5 Latches <br/>4.5 More Combinational Logic.<br/>4.5.1 Case Statements<br/>4.5.2 If Statements <br/>4.5.3 * Verilog Casez <br/>4.5.4 Blocking and Nonblocking Assignments<br/>4.6 Finite State Machines.<br/>4.7 * Parameterized Modules.<br/>4.8 Testbenches<br/>4.9 Summary.<br/>5 Digital Building Blocks.<br/>5.1 Introduction<br/>5.2 Arithmetic Circuits<br/>5.2.1 Addition<br/>5.2.2 Subtraction <br/>5.2.3 Comparators<br/>5.2.4 ALU<br/>5.2.5 Shifters and Rotators <br/>5.2.6 *Multiplication <br/>5.2.7 *Division <br/>5.2.8 Further Reading<br/>5.3 Number Systems<br/>5.3.1 Fixed-Point Number Systems<br/>5.3.2 * Floating-Point Number Systems <br/>5.4 Sequential Building Blocks.<br/>5.4.1 Counters<br/>5.4.2 Shift Registers<br/>5.5 Memory Arrays<br/>5.5.1 Overview <br/>5.5.2 Dynamic Random Access Memory (DRAM) <br/>5.5.3 Static Random Access Memory (SRAM)<br/>5.5.4 Area and Delay <br/>5.5.5 Register Files <br/>5.5.6 Read Only memory (ROM)<br/>5.5.7 Logic Using Memory Arrays <br/>5.5.8 Memory HDL<br/>5.6 Logic Arrays.<br/>5.6.1 Programmable Logic Array (PLA) <br/>5.6.2 Field Programmable Gate Array (FPGA)<br/>5.6.3 *Array Implementations <br/>5.7 Summary.<br/>6 Architecture.<br/>6.1 Introduction<br/>6.2 Assembly Language<br/>6.2.1 Instructions <br/>6.2.2 Operands: Registers, Memory, Constants<br/>6.3 Machine Language<br/>6.3.1 R-type instructions <br/>6.3.2 I-type Instructions<br/>6.3.3 J-type Instructions<br/>6.3.4 Interpreting Machine Language Code <br/>6.3.5 The Power of the Stored Program<br/>6.4 Programming<br/>6.4.1 Arithmetic / Logical Instructions <br/>6.4.2 Branching <br/>6.4.3 Conditional Statements <br/>6.4.4 Getting Loopy<br/>6.4.5 Arrays <br/>6.4.6 Procedure Calls <br/>6.5 Addressing Modes.<br/>6.6 Lights, Camera, Action: Compiling, Assembling, and Loading<br/>6.6.1 The Memory Map<br/>6.6.2 Translating and Starting a Program<br/>6.7 * Odds and Ends<br/>6.7.1 Pseudoinstructions <br/>6.7.2 Exceptions<br/>6.7.3 Signed and Unsigned Instructions <br/>6.7.4 Floating-Point Instructions <br/>6.8 * Real World Perspective: IA-32 Architecture <br/>6.8.1 IA-32 Registers <br/>6.8.2 IA-32 Operands <br/>6.8.3 Status Flags<br/>6.8.4 IA-32 Instructions<br/>6.8.5 IA-32 Instruction Encoding<br/>6.8.6 Other IA-32 Peculiarities <br/>6.8.7 The Big Picture <br/>6.9 Summary.<br/>7 Microarchitecture<br/>7.1 Introduction<br/>7.1.1 Architectural State and Instruction Set <br/>7.1.2 Design Process <br/>7.1.3 MIPS Microarchitectures <br/>7.2 Performance Analysis.<br/>7.3 Single-Cycle Processor <br/>7.3.1 Single-Cycle Datapath <br/>7.3.2 Single-Cycle Control <br/>7.3.3 More Instructions <br/>7.3.4 Performance Analysis<br/>7.4 Multicycle Processor<br/>7.4.1 Multicycle Datapath<br/>7.4.2 Multicycle Control <br/>7.4.3 More Instructions <br/>7.4.4 Performance Analysis<br/>7.5 Pipelined Processor<br/>7.5.1 Pipelined Datapath <br/>7.5.2 Pipelined Control <br/>7.5.3 Hazards <br/>7.5.4 More Instructions <br/>7.5.5 Performance Analysis<br/>7.6 * HDL Representation<br/>7.6.1 Single-Cycle Processor <br/>7.6.2 Generic Building Blocks <br/>7.6.3 Testbench <br/>7.7 * Exceptions<br/>7.8 * Advanced Microarchitecture.<br/>7.8.1 Deep Pipelines <br/>7.8.2 Branch Prediction<br/>7.8.3 Superscalar <br/>7.8.4 Out of Order<br/>7.8.5 Register Renaming <br/>7.8.6 SIMD <br/>7.8.7 Multithreading <br/>7.8.8 Multiprocessors <br/>7.9 * Real World Perspective: IA-32 Microarchitecture<br/>7.10 Summary<br/>8 Memory Systems<br/>8.1 Introduction<br/>8.2 Memory System Performance Analysis<br/>8.3 Caches<br/>8.3.1 What Data is Held in the Cache? <br/>8.3.2 How is the Data Found?<br/>8.3.3 What Data is Replaced?<br/>8.3.4 * Advanced Cache Design <br/>8.3.5 * An Evolution of MIPS Caches <br/>8.4 Virtual Memory.<br/>8.4.1 Address Translation<br/>8.4.2 The Page Table <br/>8.4.3 The Translation Lookaside Buffer (TLB)<br/>8.4.4 Memory Protection <br/>8.4.5 * Replacement Policies <br/>8.4.6 * Multilevel Page Tables <br/>8.5 * Memory-Mapped I/O.<br/>8.6 * Real World Perspective: IA-32 Memory and I/O Systems.<br/>6. 8.6.1 IA-32 Cache Systems <br/>7. 8.6.2 IA-32 Virtual Memory <br/>8. 8.6.3 IA-32 Programmed I/O <br/>8.7 Summary.<br/>9. A Digital System Implementation<br/>10. A.1 Introduction.<br/>11. A.2 74xx Logic.<br/>12. A.2.1 Logic Gates<br/>13. A.2.2 Other Functions<br/>14. A.3 Programmable Logic<br/>15. A.3.1 proms <br/>16. A.3.2 plas <br/>17. A.3.3 fpgas <br/>18. A.4 Application-Specific Integrated Circuits <br/>19. A.5 Data Sheets <br/>20. A.6 Logic Families.<br/>21. A.7 Packaging and Assembly<br/>22. A.8 Transmission lines<br/>23. A.8.1 Matched Termination<br/>24. A.8.2 Open Termination <br/>25. A.8.3 Short Termination <br/>26. A.8.4 Mismatched Termination<br/>27. A.8.5 When to use Transmission Line Models <br/>28. A.8.6 Proper Transmission Line Terminations <br/>29. A.8.7 * Derivation of Z0 <br/>30. A.8.8 * Derivation of the Reflection Coefficient <br/>31. A.8.9 Putting It All Together <br/>32. A.9 Economics.<br/>33. B MIPS Instructions<br/>
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